Conventional vertical FETs are devices in which the source-drain current is flowing in a direction perpendicular to the substrate surface. For example, if the substrate surface is made horizontal, then the vertical FET is typically a vertical pillar with the drain and source being the top and bottom portion of the pillar. One of the main advantages of the vertical FET is that the channel length is not defined by lithography, but rather by methods such as epitaxy or layer deposition which provide good thickness control even at nanometer dimensions. Some examples of vertical FET are found in Min Yang, et al., “25-nm p-channel vertical MOSFET's with SiGeC source-drains”, IEEE Electron Dev. Lett., 20, p. 301, (1999), and J. M. Hergenrother, et al., “The vertical replacement-gate (VGR) MOSFET: A 50 nm vertical MOSFET with lithography-independent gate length”, Int. Electron Dev. Meeting (IEDM), p. 75, 1999.
Conventional vertical FETs have several issues. First, it is difficult to efficiently contact the source (or drain) at the bottom of the pillar. This difficulty results in a relatively high access series resistance to the source (or drain). Second, doping cannot be achieved by implantation, but rather by in-situ doping during epitaxy, or diffusion from solid sources. Third, the gate-source capacitance is high since the gate conductor overlaps the source conductor. Fourth, the channel surface is defined by etching of the pillar or by epitaxial growth from a trench; etching typically leaves rough walls with reactive-ion etch (RIE) damage, while constrained epitaxy also exhibits defects. Fifth, fabrication of n-FETs and p-FETs devices on the same wafer for CMOS circuits requires the introduction of different dopants in the gate and the source and drain regions. This is very difficult to do because of the incompatibility with ion-implantation that is routinely used with planar FETs. Given the above challenges, prior art vertical FETs were rarely used for CMOS technology.
Recent work has shown that silicon nanowires can be used to fabricate FETs. See, for example, Yi Cui, et al., “High Performance Silicon Nanowire Field Effect Transistors”, Nano Lett., 3(2), p. 149, (2003), Andrew B. Greytak, et al., “Growth and transport properties of complementary germanium nanowire field-effect transistors”, Appl. Phys. Lett., 84(21), p. 4176, (2004), and Xiangfeng Duan, et. al, “High-performance thin-film transistors using semiconductor nanowires and nanoribbons”, Nature, 245, p. 274, (2003). As of now, reported nanowire FETs mainly used a horizontal configuration where a single nanowire was contacted by conventional lithography and back gated by applying voltage to the substrate (see, Yi Cui, et al. and Andrew B. Greytak, et al. mentioned above). In these reports, the position of the nanowires contacted to make a FET was random and their current drive was limited to a single nanowire.
Recently a horizontal (planar) thin film transistor (TFT) using a plurality of parallel nanowires that were assembled using a fluidic flow alignment approach (uniaxially compressed on a Langmuir-Blodgett) was reported. See, for example, Xiangfeng Duan, et al., “High-performance thin-film transistors using semiconductor nanowires and nanoribbons”, Nature, 245, p. 274, (2003). Yet, the issue of how to accurately position and orient nanowires for making planar nanowire FETs on a large scale is currently an open problem.
To circumvent the manipulation of nanowires, it possible to build a vertical nanowire FET, where the position of the nanowires is already determined at the time of the nanowire growth. In this case, the FET's channel consists of a plurality of nanowires to meet a specified current drive. A first report on vertical surround-gate FET using a single ZnO nanowire channel is given in Hou T. Ng, et al., “Single Crystal Nanowire Vertical Surround-Gate Field-Effect Transistor”, Nano Lett., 4(7), p. 1247, (2004).
The Hou T. Ng, et al. paper does not address the main deficiencies associated with vertical MOSFETs, which are how to reduce the access resistance to the bottom contact, and how to accurately control the gate length. Additionally, the Hou T. Ng, et al. paper does not address how to use a plurality of nanowires in the fabrication of the MOSFET.
In view of the foregoing, there is a need for providing a vertical FET which includes a plurality of nanowire channels in which the access resistance to the bottom contact is reduced and where the gate length is controlled.